Fusion SoC: A Fused-Grained Reconfigurable Architecture for Efficient Edge Computing Acceleration

With the demise of Dennard scaling and the looming end of Moore’s law, architects scale the inefficient single-core CPU to multi-core CPUs to optimize performance. However, even multi-core CPUs are now nearing their performance limits due to the power wall. Therefore, the above limitations have spurred the rapid advancement of accelerators in various domains. Among the prevailing accelerators, Reconfigurable Architecture emerges as a formidable contender due to its post-silicon reconfigurability and the potential to approach application-specific integrated circuit (ASIC)-like energy-efficiency and performance.

In this workshop, we will introduce an open-source development framework for Reconfigurable Architecture, which covers the entire reconfigurable architecture development from the front-end compilation to ASIC implementation, enabling the architecture exploration at different stages in the software toolchain. For the front-end compilation, Fusion has two front-end tools, including: (1) the MLIR-based tool to compile the emerging applications, such as various deep neural networks; (2) the LLVM-based tool for more general-purpose, loop-kernel level compilation. Within the Fusion SoC, there is a RISC-V CPU and a Fused-Grained Reconfigurable Architecture (FGRA), which provides efficient acceleration for different computation-intensive kernels. Moreover, the Fusion SoC is a highly parameterized design, allowing for customization for specific applications through a design space exploration process based on Bayesian optimization. With several innovative optimizations, the Fusion SoC can significantly improve performance for computation-intensive systems.

We hope you enjoy the workshop and look forward to your valuable feedback.